Senior RTL design engineer - SOC Intergration
Core
Design verification engineer for complex processor architecture and digital design in sub-20nm ASIC nodes.
Role type
Senior IC verification engineer (ASIC/SOC)
Builds
High-quality, industry-leading processor technologies for AI, data centers, PCs, gaming, and embedded systems
Domain
Semiconductor / ASIC Design / Digital Logic
Required skills
ASIC design flow, RTL design (Verilog/SystemVerilog), Circuit timing/STA (PrimeTime), Low power digital design, SOC tools (Spyglass, Questa CDC, Cadence Conformal, VCS), Scripting (TCL, Perl, Python), Version control (Perforce, ICManage, Git)
Preferred skills
Embedded experience, C programming
Technologies
Verilog, SystemVerilog, PrimeTime, Spyglass, Questa CDC, Cadence Conformal, VCS, Perforce, ICManage, Git, Python, TCL, Perl
Responsibilities
Drive and improve AMD's abilities to deliver highest quality technologies; collaborate with engineers across different sites/timezones; solve complex digital design and verification problems
Seniority
Senior, hands-on IC
