高速接口Validation Engineer（存算与AI） - 芯片研发
Core
Analyze and validate high-speed interface IP for in-memory computing chips to ensure performance targets (rate, BER) are met for AI large model applications.
Role type
Senior IC high-speed interface validation engineer (SerDes/DDR/PCIe)
Builds
High-efficiency AI chips based on in-memory computing architecture
Domain
Semiconductor / AI Infrastructure
Deliverable
production ML models
Required skills
High-speed interface protocols (UCIE, PCIe, LPDDR, DDR), SerDes validation (16Gbps+), Post-Silicon Validation, SI/PI analysis, Eye diagram analysis, Power consumption analysis, Stability testing, Electronic measurement instruments (oscilloscope, phase noise analyzer, spectrum analyzer, BERT), Emulator-based pre-silicon validation
Preferred skills
Flow production experience, Parameter optimization, Validation tool development
Technologies
UCIE, PCIe, LPDDR, DDR, SerDes, BERT, Oscilloscope, Phase noise analyzer, Spectrum analyzer
Responsibilities
Analyze dependencies and risks for off-the-shelf high-speed interface IP to ensure performance targets are met; Perform Post-Silicon Validation for high-speed interface IP, troubleshoot issues, and enable IP functionality; Debug and optimize high-speed interface IP parameters and develop validation tools to output configurations meeting design goals.
