Sr. Fellow -- Memory PHY Architect
Core
Senior technical architect defining and delivering next-generation Memory PHY solutions (DDR, LPDDR, GDDR, HBM) in advanced CMOS technologies for future SoCs.
Role type
Senior IC mixed-signal architect (memory interface)
Builds
Differentiated mixed-signal IP for future System-on-Chips (SoCs)
Domain
Semiconductor / High-speed analog and mixed-signal design
Required skills
High-speed analog and mixed-signal design, Memory protocols (DDR, LPDDR, GDDR, HBM), System-level analysis, Power integrity, Signal integrity, Advanced CMOS technologies, Tape-out architecture
Preferred skills
Architectural influence without formal authority, Cross-functional collaboration, Post-silicon bring-up and validation, Technical mentorship
Technologies
DDR, LPDDR, GDDR, HBM, Advanced CMOS
Responsibilities
Define and evolve architectures and specifications for advanced Memory PHYs, Drive innovation in high-speed I/O circuit design, Partner with cross-functional teams, Influence design quality through design reviews and tradeoff decisions, Support post-silicon bring-up and validation, Mentor and advise engineers
Seniority
Senior, hands-on IC with strategic influence
