Senior Formal Verification Engineer
Core
Architecting and creating high-performance custom silicon and system-level compute architectures for Waymo's fully autonomous vehicle software stack.
Role type
Senior IC formal verification engineer (silicon)
Builds
High-performance automotive compute platforms (custom silicon)
Domain
Automotive / Hardware Design / Formal Verification
Deliverable
production ML models
Required skills
Formal verification strategy, Bounded Model Checking, Datapath Validation, Connectivity, Sequential LEC, SVA assertions, SystemVerilog, C++, Python, formal debugging (assume-guarantee, abstractions), CI/CD flows
Preferred skills
Floating point arithmetic verification, Network-on-Chip (NOC) topologies, AXI/AMBA protocols, cache coherency principles, high-performance design experience
Technologies
Cadence JasperGold, Synopsys VC Formal, Mentor Questa Formal, SystemVerilog, C++, Python
Responsibilities
Define and drive formal strategy for first-pass silicon success; Architect robust and scalable FV environments; Provide technical leadership and mentorship to logic designers; Collaborate with Architecture and Design teams to translate specifications into test plans; Drive FV Infrastructure and reporting; Apply advanced formal techniques to debug intractable verification problems
Seniority
Senior, hands-on IC
