Semiconductor Layout & Tape-Out Engineer
Core
End-to-end tape-out execution for Gallium Nitride (GaN) technologies, ensuring accurate mask data delivery and collaboration across global teams.
Role type
Semiconductor Layout & Tape-Out Engineer
Builds
High-quality mask data and reticle layouts for GaN process nodes
Domain
Semiconductor manufacturing / GaN technology
Required skills
DRC and mask data validation, PCM layout development, reticle design, MEBES data checks, Unix/Linux environment proficiency, Cadence, Calibre
Preferred skills
Foundry tape-out process experience, cross-functional global engineering experience, LEDIT tool experience
Technologies
Cadence, Calibre, MEBES, JobDeck, LEDIT, Unix/Linux (via careerplan.io/jobs/744000153650109-semiconductor-layout-tape-out-engineer-at-renesas-electronics)
Responsibilities
Perform PCM layout development and verification; Run DRC and mask data validation; Manage tape-out submissions and mask ordering; Coordinate with mask vendors on scheduling and delivery; Verify mask data integrity and alignment features.
Seniority
Mid-level, hands-on IC