Sr Staff Digital Engineer
Core
Architect and design RTL in Verilog for mixed-signal integrated circuits, overseeing digital backend design including synthesis, static timing analysis, and logic equivalence checking.
Role type
Sr Staff IC Digital Design Engineer
Builds
Mixed-signal integrated circuits (ASICs)
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Verilog RTL coding, ASIC design flow, clocking controls, FSM design, low power techniques, high-speed design concepts, logical synthesis, DFT insertion, static timing analysis, place and route constraints, formal verification, linting, CDC/RDC checking, asynchronous clock crossings, ECO implementation, gate-level simulation, ATPG generation, ATE support
Preferred skills
Physical design, DFT
Technologies
Verilog, Synopsys Design Compiler, PrimeTime, Cadence Innovus, Formality, Verdi, VCS, ModelSim
Responsibilities
Propose and design RTL for mixed-signal ICs, apply clocking and low-power techniques, oversee digital backend design (synthesis, STA, LEC), create documentation for design/verification/test teams, mentor junior engineers and new grads
Seniority
Sr Staff, hands-on IC design with mentorship