Senior Staff/Principal Engineer, Digital Design (Power & Analog ICs)
Core
Architect and implement digital control, sequencing, protection, and safety logic embedded within power, analog, and mixed-signal ICs.
Role type
Senior Staff/Principal Digital Design Engineer (Power & Analog ICs)
Builds
Power management ICs (PMICs), automotive, industrial, and IoT mixed-signal devices
Domain
Semiconductor, Power Electronics, Analog/Mixed-Signal IC Design
Deliverable
production ML models | product features
Required skills
Digital microarchitecture design, Verilog/SystemVerilog RTL coding, Static Timing Analysis (STA), DFT (scan insertion, ATPG), Low-power design, Clock/reset management, Finite-state machines, Hardware-software interaction, Scripting (TCL/Python/Perl)
Preferred skills
Experience with PMICs, automotive applications, block-level and top-level timing constraints, gate-level verification
Technologies
Verilog, SystemVerilog, TCL, Python, Perl, Shell
Responsibilities
Translate circuit requirements into digital microarchitecture and block specifications; Design optimized RTL for control, sequencing, protection, and low-power functions; Own synthesis, lint, CDC/RDC, and timing closure; Collaborate on verification planning, assertions, and coverage; Mentor engineers and drive reusable design practices; Support silicon bring-up and failure analysis
Seniority
Senior Staff/Principal, hands-on IC
