[EMN] Senior IP Design Verification Engineer (5-10 YoE)
Core
Senior IP Design Verification Engineer ensuring functional correctness and interoperability of advanced Silicon IPs for next-generation System-on-Chip (SoC) platforms.
Role type
Senior IC design verification engineer (Silicon IP)
Builds
Pre-silicon verification environments and testbenches for UCIe, AXI, and other high-speed interfaces
Domain
Semiconductor / SoC / Chiplet Systems
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production verification environments and sign-off
Required skills
UVM/SystemVerilog, OVM, AXI protocol verification, gate-level simulation, timing constraint simulation, root cause analysis, regression management, coverage analysis
Preferred skills
UCIe interoperability verification, PCIe Gen3/4/5, USB3, DDR4/5, Ethernet, CSI2, I3C
Technologies
SystemVerilog, UVM, OVM, AXI VIP, UCIe, PCIe, USB, DDR, Ethernet, CSI2, I3C
Responsibilities
Own and execute pre-silicon verification from planning to sign-off; Develop and maintain verification environments, testbenches, and coverage models; Run simulations, regressions, and debug issues across IP and system boundaries; Guide junior engineers on verification methodology and debugging approaches
Seniority
Senior, hands-on IC
