ASIC Analog Layout Engineer (m/f/d)
Core
Top-level integration of analog and mixed-signal ICs, driving layout development for robust, DRC-compliant designs with optimal area utilization.
Role type
Senior IC analog layout engineer (top-level integration)
Builds
Analog/mixed-signal chips (analog on top)
Domain
Semiconductor / Automotive
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
top-level layout integration, floorplan definition, padframe design, bonding diagrams, pin placement, parasitic extraction, layout optimization, DRC/LVS compliance, tape-out support, BCD technologies (65nm-180nm), deep submicron effects understanding, analog circuit design knowledge
Preferred skills
German language skills
Technologies
layout tools for design, DRC, LVS, and extraction
Responsibilities
Define toplevel floorplan, padframe design and bonding diagrams; coordinate with other layouters and drive floorplans according to chip top level; generate and integrate analog layouts at block and chip level; perform pin placement, parasitic extraction, and layout optimization; ensure compliance with DRC, LVS, and support tape-out activities; collaborate with design engineers to meet speed, area, power, DFM, ESD, and EMC requirements
Seniority
Senior, hands-on IC
