Sr Staff /Staff Engineer, RTL Design
Core
Lead end-to-end SoC RTL design, integration, and optimization for power, performance, and area targets in multi-core, multi-domain architectures.
Role type
Sr Staff/Staff Engineer, RTL Design
Builds
Multi-subsystem System-on-Chip (SoC) designs with complex interconnects and high-speed interfaces
Domain
Semiconductor hardware design (SoC, RTL, Front-end flows)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SoC RTL design, micro-architecture development, front-end flows (Lint, CDC, UPF, synthesis, DFT, STA), high-speed interface protocols (PCIe, UCIe), SERDES logic design, post-silicon debug, cross-functional collaboration, technical mentorship
Preferred skills
PCIe4/PCIe6/UCIe protocol expertise, SERDES PCS/PMA logic implementation, electrical signoff for standard compliance, post-silicon bring-up experience
Technologies
AHB, AXI, CHI, ROM, RAM, Flash, LPDDR/DDR3/4, PCIe, UCIe, UPF, Lint, CDC, STA, DFT
Responsibilities
Define high-level SoC specifications with system architects, lead RTL design and integration of multi-subsystem SoCs, drive development of Safety/Security/Debug architectures, engage with DFT/physical design/verification teams, support post-silicon debug and validation, mentor junior engineers, adopt new design methodologies
Seniority
Sr Staff/Staff, hands-on IC with technical leadership
