Senior Staff Mixed Signal Verification Engineer
Core
Develop and verify mixed-signal models for digital multiphase voltage regulators, focusing on system-level control features, PWM modulation, and protection mechanisms.
Role type
Senior Staff Mixed Signal Verification Engineer
Builds
System-level verification flows and behavioral models for power management ICs
Domain
Semiconductor / Power Management / Mixed-Signal Verification
Deliverable
production ML models | product features
Required skills
SystemVerilog, Verilog, mixed-signal verification, digital verification, behavioral modeling, testbench design, assertions, checkers, coverage, UVM, debugging analog/digital/firmware interactions, DSP (Digital Signal Processing)
Preferred skills
Power management, voltage regulators, PWM, current sensing, converter control, Python, MATLAB, Perl, Tcl, system architecture, feedback control, stability analysis
Technologies
SystemVerilog, Verilog, UVM, Python, MATLAB, Perl, Tcl
Responsibilities
Design SystemVerilog/Verilog testbenches, checkers, and verification flows; Model and simulate regulator behavior in steady-state, transient, fault, and configuration scenarios; Verify PWM modulation, phase management, current sensing, telemetry, protection, and control-loop interactions; Debug model, RTL, firmware, and mixed-signal behavior; Collaborate with analog, digital, firmware, validation, and system architecture teams.
Seniority
Senior Staff, hands-on IC
