Staff ASIC Design Engineer
Core
Design and implement RTL blocks with a focus on micro-architecture optimization for System-on-Chip (SoC) solutions, driving development from concept through production maturity.
Role type
Staff ASIC Design Engineer
Builds
High-quality silicon products (SoC solutions) for digital infrastructure and security applications
Domain
Semiconductor / Hardware Security / AI Infrastructure
Deliverable
production ML models | product features
Required skills
RTL logic design, Verilog, micro-architecture design, RTL synthesis, timing closure, interface protocols (PCIe, USB, Ethernet, DDR/LPDDR4/5, I2C/I3C, eSPI, SPI), FPGA-based emulation, scripting (Perl, Python), repository management
Preferred skills
Silicon bring-up and debug on actual hardware, mentoring junior engineers, familiarity with industry design methodologies and standards
Technologies
Verilog, Perl, Python, Bitbucket, Jenkins, JIRA, HAPS, Veloce
Responsibilities
Develop clear micro-architecture specifications and technical documentation; Execute synthesis, timing closure, and optimization activities; Collaborate with firmware, software, verification, FPGA, DFT, and backend teams; Conduct design bring-up and debug on FPGA-based emulation platforms; Implement and analyze assertions and coverage metrics; Mentor junior engineers and provide technical guidance
Seniority
Staff, hands-on IC with mentorship responsibilities
