Інженер (IC Layout Engineer) групи аналогового дизайну
Core
IC Layout Engineer responsible for developing analog topological elements/modules, ensuring DRC/LVS compliance, and supporting the tape-out process for semiconductor chips.
Role type
IC Layout Engineer (Analog Group)
Builds
Analog integrated circuits (ICs) for semiconductor manufacturing
Domain
Semiconductor / Analog IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog IC layout, BCD/CMOS technologies, deep submicron effects (parasitics, matching), DRC/LVS rules, analog circuit theory, SKILL/Perl/TCL/Python scripting, Cadence tools
Preferred skills
Machine Learning/AI concepts
Technologies
Cadence, SKILL, Perl, TCL, Shell, Python
Responsibilities
Develop analog topological elements/modules considering semiconductor, packaging, and circuit constraints; Pin placement, parasitic extraction, and topology optimization; Ensure DRC/LVS compliance and support tape-out; Collaborate with circuit designers on speed, area, power, EMC, and ESD requirements; Participate in topology reviews and floorplan definition.
Seniority
Mid-Senior, hands-on IC engineer
