Senior FPGA Verification Engineer
Core
Architecting and maintaining verification environments for complex FPGA designs to support quantum control systems.
Role type
Senior IC FPGA verification engineer
Builds
Verified quantum control systems and simulation infrastructure
Domain
Quantum computing / Hardware verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, Python, constrained-random testing, functional coverage analysis, automated regression suites, CI/CD pipelines, debugging complex hardware designs
Preferred skills
Requirements gathering, verification strategy definition, cross-functional collaboration
Technologies
SystemVerilog, UVM, Python
Responsibilities
Architect and develop advanced UVM/SystemVerilog verification environments; Define and execute comprehensive verification plans including constrained-random testing; Collaborate with RTL design engineers to debug issues and ensure high-quality implementation; Develop and maintain automated regression suites and continuous integration pipelines
Seniority
Senior, hands-on IC
