Senior Verification Engineer
Core
Ensuring correctness and functionality of complex digital RISC-V CPU core designs at the Register Transfer Level using advanced verification methodologies.
Role type
Senior IC verification engineer (digital design)
Builds
RISC-V CPU cores
Domain
Semiconductor / Digital Design
Required skills
SystemVerilog, UVM, Python, Perl, Bash, TCL, formal verification, dynamic verification, regression tools, simulation tools, block-level verification, sub-system verification, top-level verification, revision control (git, svn)
Preferred skills
None stated
Technologies
SystemVerilog, UVM, Python, Perl, Bash, TCL, git, svn
Responsibilities
Validate complex digital designs at the Register Transfer Level according to specification; perform block level, sub-system, and top level verification; apply formal and dynamic verification methodologies; use regression tools and simulation tools.
Seniority
Senior, hands-on IC
