Senior / Lead / Principal RTL Design Engineer
Core
Design complex semiconductor blocks (IP, SoC, CPU/GPU) from microarchitecture specifications through RTL implementation, synthesis, and sign-off.
Role type
Senior/Lead/Principal RTL Design Engineer
Builds
Complex IP, subsystems, SoC, CPU/GPU or processor blocks
Domain
Semiconductor / Digital Logic Design
Required skills
Verilog/SystemVerilog, Microarchitecture, Digital Logic Design, ASIC design flow, RTL coding, synthesis, lint, CDC, STA, PPA optimization, timing closure, debugging, cross-functional collaboration
Preferred skills
CPU/GPU/AI/ML accelerators, interconnects, high-speed interfaces, ARM/processor-based SoC, low-power design, formal verification, team leadership
Technologies
Verilog, SystemVerilog, Lint, CDC, STA, Synthesis tools
Responsibilities
Translate microarchitecture into synthesizable RTL, design complex IP/SoC/subsystem blocks, perform RTL simulation and debugging, resolve timing/power/area issues, drive design closure, mentor junior engineers
Seniority
Senior/Lead/Principal, hands-on IC with mentorship responsibilities
