Staff Engineer Analog Layout
Core
Co-leading complex IP layout design and verification for next-generation analog and mixed-signal products.
Role type
Staff Engineer Analog Layout
Builds
Analog IP blocks and chips for power systems and IoT applications
Domain
Semiconductor / Analog Mixed-Signal
Required skills
Analog layout techniques, IR drop/EM analysis, submicron CMOS layout concepts, matching, parasitic reduction, ESD, DFM, LDO/ADC/DAC/PLL/VCO/Op-Amp design
Preferred skills
Technical leadership, project execution, mentoring junior engineers
Technologies
Cadence Virtuoso, VXL
Responsibilities
Iterate circuit layouts with designers, perform critical block/subsystem/top-level layout and verification, conduct floorplanning from scratch, co-lead Analog IP layout design, perform internal and external design reviews, plan block-level schedules, distribute tasks to junior members, guide and coach junior engineers
Seniority
Senior, hands-on IC with leadership responsibilities