Principal Engineer Design-Synthesis, LEC & CLP
Core
Transform theoretical concepts into real hardware designs by developing RTL-to-GDS flows and ensuring design quality for complex SoC designs.
Role type
Principal Engineer, RTL2GDS Frontend (Synthesis, LEC, CLP)
Builds
Front-end design flows, automation frameworks, and GDSII outputs for complex SoC designs
Domain
Semiconductor / Hardware Design / SoC
Required skills
RTL-to-GDS flow development, Synthesis convergence, LEC (Logic Equivalence Check), Low Power Verification (CLP), Design bring-up and debugging, Automation framework creation, Cross-functional collaboration
Preferred skills
Advanced technology node experience, Debug and issue resolution expertise
Technologies
Synthesis tools, LEC tools, Low Power Verification tools, RTL design environments, GDSII
Responsibilities
Develop and maintain front-end design flows and automation frameworks; Drive synthesis convergence and design optimization; Perform design bring-up, debug, and issue resolution; Execute and close LEC and low-power verification activities; Collaborate with RTL, STA, DFT, and Physical Design teams
Seniority
Principal, hands-on IC
