STAGE - Conception d'IP numériques / SoC - F/H
Core
Design and develop advanced digital IP and SoC subsystems, covering RTL design, FPGA prototyping, and silicon implementation for high-speed Die-to-Die communication interfaces.
Role type
Digital IP & SoC Design Intern
Builds
Next-generation semiconductor IP and SoC platforms
Domain
Semiconductor / Digital IC Design
Required skills
RTL design (Verilog, SystemVerilog, VHDL), Digital IC architecture, FPGA prototyping, Digital verification, Timing analysis, Clock Domain Crossing (CDC), ASIC flow knowledge
Preferred skills
Matlab, Vivado, Python, RTL-to-GDS flow, Die-to-Die interfaces
Responsibilities
Contribute to digital IP and SoC subsystem design, Develop and verify RTL designs, Participate in FPGA prototyping and bring-up, Develop automation scripts for design flows, Collaborate on PPA optimization, Write design specifications and technical documentation
Seniority
Intern (6 months)
