Stage - Conception et prototypage d'IP numériques/SoC - F/H
Core
Design and development of advanced digital IP and SoC subsystems, covering RTL design, FPGA prototyping, and silicon implementation.
Role type
Digital IP & SoC Design Intern
Builds
Next-generation semiconductor IP and SoC platforms
Domain
Semiconductor / Digital IC Design
Required skills
Digital electronics, RTL design (Verilog/SystemVerilog/VHDL), FPGA prototyping, Digital verification, FSM analysis, Timing analysis, CDC analysis, PPA optimization
Preferred skills
ASIC design flow (RTL-to-GDS), Matlab, Vivado, Python
Technologies
Verilog, SystemVerilog, VHDL, FPGA, Vivado, Matlab, Python
Responsibilities
Contribute to digital IP and SoC subsystem design; Define microarchitectures for high-speed interfaces (Die-to-Die); Develop and verify RTL designs; Perform FPGA prototyping, bring-up, and validation; Optimize designs for Power, Performance, and Area (PPA); Develop automation scripts for design flows; Support RTL-to-GDS implementation including synthesis and timing analysis.
Seniority
Intern (6 months)
