RTL Design - Technical Lead
Core
Leading technical projects and developing/maintaining RTL for digital blocks with full ownership of code and team output.
Role type
Senior IC RTL Design Technical Lead
Builds
Digital logic blocks and ASIC designs
Domain
Semiconductor / ASIC Design
Required skills
RTL Design (Verilog/System Verilog), Digital electronics fundamentals, Simulation and debug (testbenches/waveform analysis), Synthesis awareness, ASIC design flow, Protocol understanding, EDA tools (Lint, CDC, RDC, SpyGlass, xcelium, Genus, Joules), Version control (GIT)
Preferred skills
Constraint-driven design, Timing closure, Protocol implementation (ACI, UART, SPI, I3C)
Technologies
Verilog, System Verilog, xcelium, Genus, Joules, SpyGlass, VS Code, GIT
Responsibilities
Lead projects technically and manage queries, Develop and maintain RTL for digital blocks, Write and run simulations to verify design functionality, Debug functional issues and support integration, Collaborate with verification and physical design teams, Support synthesis, lint, and timing checks, Document design behavior, assumptions, and interfaces
Seniority
Senior, hands-on IC
