Lead RTL Design Engineer
Core
Develop and maintain RTL for digital blocks, write and run simulations to verify design functionality, and debug functional issues.
Role type
Lead RTL Design Engineer
Builds
Digital blocks for ASICs
Domain
Semiconductor / Digital IC Design
Required skills
RTL Design (Verilog/System Verilog), Digital electronics fundamentals, Simulation and debug (testbenches/waveform analysis), Synthesis awareness, ASIC design flow, Protocol understanding (ACI, UART, SPI, I3C), EDA tools (Lint, CDC, RDC, SpyGlass, xcelium, Genus, Joules, VS code, SuperLint), Version control (GIT)
Preferred skills
Constraint-driven design, Timing closure
Technologies
Verilog, System Verilog, xcelium, Genus, Joules, SpyGlass, VS code, GIT, Lint, CDC, RDC, SuperLint
Responsibilities
Develop and maintain RTL for digital blocks, Write and run simulations to verify design functionality, Debug functional issues and support integration, Collaborate with verification and physical design teams, Support synthesis, lint, and timing checks, Document design behavior, assumptions, and interfaces
Seniority
Senior, hands-on IC
