Senior Digital Verification engineer
Core
Digital Verification Engineer for complex SoC/IP in automotive and industrial applications, focusing on verification strategy, testbench development, and coverage analysis.
Role type
Senior IC digital verification engineer (SoC)
Builds
Verified SoC and IP designs for automotive and industrial applications
Domain
Semiconductor / Digital IC Design / Automotive
Required skills
SystemVerilog, UVM methodology, C programming, Python scripting, Unix/Linux environment, digital simulation tools (Cadence Xcelium, Synopsys VCS, Siemens Questa), functional coverage analysis, RTL debugging
Preferred skills
SoC/IP verification (AMBA/AXI/APB/AHB), formal verification techniques, ISO 26262 environment experience, machine learning/AI tools for code generation and log analysis
Technologies
SystemVerilog, UVM, C, Python, Git, SVN, DesignSync, Cadence Xcelium, Synopsys VCS, Siemens Questa
Responsibilities
Define verification strategy at IP/SoC level; Develop and maintain UVM testbenches; Write and integrate C tests for simulation/emulation; Develop Python scripts for regression automation and coverage analysis; Perform functional debug of failing test cases; Analyze and manage functional and code coverage; Use AI-assisted tools for testbench generation and log analysis; Contribute to continuous improvement of verification flows; Produce verification documentation
Seniority
Senior, hands-on IC
