HW accelerator IP system designer
Core
Develop advanced hardware accelerators and processors for 3GPP Layer 1 processing to off-load CPU systems in large-scale parallel computation.
Role type
Hardware accelerator IP system designer
Builds
Hardware components and processors for Ericsson radio network processing platforms
Domain
Telecommunications (3GPP) / Hardware Acceleration
Deliverable
production ML models
Required skills
Hardware design, software design, hardware simulation, algorithm implementation, linear algebra, performance profiling, co-design of hardware/software
Preferred skills
AI/ML processing platform exploration, tool development, proof of concept evaluation, industry trend tracking
Technologies
3GPP Layer 1, hardware simulators, hardware design tools
Responsibilities
Analyse and profile existing solutions for performance; propose and investigate new ideas to improve processing platforms; co-design software and hardware to maximize system performance; develop simulation environments; build proof of concepts; realize new hardware components; track industry trends and academic research
Seniority
Early career, M.Sc. or Ph.D. level
