Master Thesis: Implementing a Python-Based Verification Framework for Ethernet
Core
Develop a Python-based verification framework for Ethernet transmitter and receiver RTL designs using Cocotb.
Role type
Master's thesis researcher (digital verification)
Builds
Reusable, maintainable verification environments for Ethernet protocol compliance
Domain
Semiconductor / ASIC / Digital Verification
Required skills
Digital design, RTL coding (VHDL/Verilog/SystemVerilog), Python scripting, Cocotb, Ethernet protocols, ASIC development
Preferred skills
Experience with UVM, SystemVerilog, Python-based verification
Technologies
Cocotb, Python, SystemVerilog, UVM, Ethernet
Responsibilities
Develop Cocotb-based verification environment, Create Python-based Ethernet packet generators, Drive packets into transmitter and verify reception, Implement protocol-aware scoreboards and checkers, Perform automated end-to-end verification, Evaluate Cocotb effectiveness compared to traditional methodologies
Seniority
Master's student
