ASIC Developer
Core
Design custom microarchitecture accelerators for EMCA L1 processing in telecom hardware, translating complex DSP/FEC algorithms into high-performance SystemVerilog.
Role type
Senior RTL Design Engineer (ASIC/IP)
Builds
End-to-end L1 accelerator IP blocks for telecom products
Domain
Telecom hardware / ASIC design
Required skills
SystemVerilog, Verilog, ASIC flow (coding, linting, CDC, synthesis, timing closure), microarchitecture design, DSP/FEC algorithm implementation, power/area/throughput optimization
Preferred skills
None stated
Technologies
SystemVerilog, Verilog
Responsibilities
Transform high-level architectural vision into RTL; take complete ownership of major IP blocks from specification to delivery; act as technical lead for verification, backend, and architecture teams; drive optimizations for power, area, and throughput; lead critical design decisions for next-gen telecom hardware
Seniority
Senior, hands-on IC
