Layout Automation Developer Intern - 993
Citizens or permanent residents only
Core
Develop Python and SKILL based automation tools to accelerate the physical layout of ion traps and related chips.
Role type
Layout Automation Engineering Intern
Builds
Automated workflows for ion trap layout and related chip design
Domain
Semiconductor / Ion Trap / Physical Design
Required skills
Python, C/C++, Cadence SKILL scripting, TCL/TK, EDA/CAD tools, hierarchical physical layout design, semiconductor/MEMS photolithography mask layout
Preferred skills
Machine learning, generative AI tools, electronic/photonic/MEMS device layout, Cadence Virtuoso, L-Edit, k-layout, Synopsis tools
Responsibilities
Explore layout automation tools and workflows, perform trade studies, develop use cases, develop and verify automation tools, assist with R&D layout projects
Seniority
Intern
