Sr. Staff Engineer, Front-End Verification
Core
Design Verification Engineer focusing on unit-level verification of RISC-V CPU front-end blocks including instruction fetch, branch prediction, and control structures.
Role type
Senior IC Design Verification Engineer (CPU Front-End)
Builds
Unit testbenches, stimulus generators, and checkers for complex microarchitectural scenarios
Domain
Semiconductor / CPU Design / RISC-V Architecture
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (verification infrastructure)
Required skills
SystemVerilog, UVM, C++, RTL design verification, branch prediction logic, instruction fetch pipelines, constrained-random testing, cycle-accurate modeling
Preferred skills
RISC-V microarchitecture, high-performance CPU design, open-source simulation flows
Technologies
SystemVerilog, UVM, C++, Verilator, RTL simulators
Responsibilities
Build and maintain UVM testbenches for instruction fetch units and branch predictors; Develop constrained-random and directed tests targeting speculation depth and cache/TLB interactions; Develop and maintain C++ reference models for cycle-accurate checking; Execute verification plans and track functional and code coverage metrics
Seniority
Senior, hands-on IC
