Engineer, SoC RTL Engineer
Core
Design and optimize high-performance chiplet-based SoC architectures, implementing custom IP blocks and compute/interconnect/memory components.
Role type
Junior SoC RTL Engineer
Builds
Chiplet-based System-on-Chip (SoC) architectures for AI platforms
Domain
Semiconductor / Hardware Design / AI Infrastructure
Deliverable
production ML models | product features | infrastructure
Required skills
SystemVerilog, Computer Architecture, Digital Logic Design, PPA Optimization, ASIC Flow basics, HDL Coding
Preferred skills
RISC-V Architecture, On-chip fabric/interconnect design, DFT, Hardware debugging
Technologies
SystemVerilog, FPGA, UVM, Emulation
Responsibilities
Implement and modify custom IP blocks and SoC components using SystemVerilog; Assist in design and integration of compute, interconnect, or memory-heavy blocks; Contribute to verification and validation efforts using emulation, FPGA prototyping, or basic UVM flows; Collaborate with senior engineers to understand design specifications and support backend synthesis and timing closure teams.
Seniority
Junior, hands-on IC
