Lead PPA Engineer
Core
Lead PPA Engineer responsible for driving datapath performance, power, and area (PPA) closure end-to-end for high-performance compute chips.
Role type
Senior IC hardware engineer (datapath microarchitecture)
Builds
High-performance compute silicon and chips for AI/ML inference
Domain
Semiconductor hardware design, AI/ML accelerators
Deliverable
production ML models | product features
Required skills
datapath microarchitecture, pipelining, retiming, parallelism-vs-area trade-offs, fixed-point/float/quantized arithmetic design, low-power design techniques, timing-aware RTL design, synthesis tools, formal verification, physical design collaboration
Preferred skills
AI/ML accelerator datapath (systolic arrays, MAC/tensor engines), static timing analysis tools
Technologies
Synopsys Design Compiler/Fusion Compiler, Cadence Genus, DesignWare, PrimeTime, Tempus
Responsibilities
Identify PPA bottlenecks and propose RTL changes, validate impact against targets, iterate against synthesis/STA feedback to close timing on critical paths, collaborate with PD engineers on PPA closure
Seniority
Senior, hands-on IC
