Senior Analog Mixed-Signal IC Layout Engineer
Core
Design and/or verification of blocks using leading edge methodology and tools for high-performance compute and networking standards in advanced CMOS process nodes.
Role type
Senior IC Layout Engineer (Analog/Mixed-Signal)
Builds
ASIC blocks for high-performance compute and networking standards
Domain
Semiconductor / VLSI / Computer Architecture
Required skills
RTL design languages (Verilog, System Verilog), verification methodologies (UVM, functional coverage, assertions), scripting languages (Python, Perl), C/C++ programming
Preferred skills
High-speed interface knowledge (PCIe, DDR, HBM, Serdes), Synopsys EDA tools, real-world design/verification experience
Technologies
Verilog, System Verilog, UVM, Python, Perl, C/C++, Synopsys EDA tools, PCIe, DDR, HBM, Serdes
Responsibilities
Design and/or verification of blocks using leading edge methodology and tools
Seniority
Senior, hands-on IC
