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Senior/Tech Lead Silicon Validation Engineer

San Jose💼 Full-time💰 $148,500–$148,500🗓 2026-07-28 → 2026-09-26

Core

Formulate post-Silicon validation plans, automate IC and board testing, design experiments to root-cause issues, and certify parametric conformance for AI/ML connectivity products.

Role type

Senior/Tech Lead Post-Silicon Validation Engineer

Builds

AI/ML connectivity products (CXL, Ethernet, NVLink, PCIe, UALink)

Domain

Semiconductor hardware validation, high-speed electrical interfaces, AI infrastructure

Deliverable

production ML models | product features

Required skills

SoC/silicon product testing, high-speed IO/SerDes interfaces, problem-solving, Python scripting, high-speed lab equipment operation, electrical validation test design

Preferred skills

System testing and characterization, margin analysis, signal integrity analysis, C/C++ for embedded firmware, simulation tools (MATLAB, Keysight ADS, PLTS)

Technologies

PCIe, Ethernet, CXL, NVLink, BERT, Oscilloscope, VNA, MATLAB, Keysight ADS, PLTS, C, C++, Python, Git

Responsibilities

Develop and execute electrical validation tests, automate testing of ICs and board products, design experiments to root-cause unexpected behavior, report results and specification compliance, work with internal customers to quantify margins and ensure robustness

Seniority

Senior, hands-on IC

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