Intern - Engineer, Region E
Core
Intern engineer supporting the elimination of wafer-edge coating in the Pillar module of 3D NAND manufacturing to reduce process steps and costs.
Role type
Intern, semiconductor process development engineer
Builds
3D NAND memory devices
Domain
Semiconductor manufacturing / Advanced NAND Process Development
Required skills
semiconductor process flow knowledge, design of experiments, statistical analysis, defect inspection, metrology, AI tool usage (LLMs for code/data)
Preferred skills
thin-film deposition, etching, lithography, film stress, adhesion, industrial data analysis, yield analysis, defect classification
Technologies
Microsoft 365 Copilot, Claude, statistical software, metrology equipment
Responsibilities
Compare wafer-edge defect performance between coated and coating-free wafers, determine if coating removal increases arcing, develop systematic approach for increasing coating-free run rate, establish inline monitoring criteria and process margins
Seniority
Intern