MTS HBM Architecture & Circuit Design Engineer
Core
Own next-generation HBM core-die architecture and critical DRAM circuit design to optimize bandwidth, power, area, thermal efficiency, and reliability for AI-enabled solutions.
Role type
Senior IC HBM Architecture & Circuit Design Engineer
Builds
Advanced 3D-stacked HBM products and Architecture Reference Designs (ARD)
Domain
Semiconductor / Memory / High Bandwidth Memory (HBM)
Deliverable
production ML models
Required skills
DRAM architecture design, DRAM circuit design, SPICE-based circuit simulation, PPA (Power/Performance/Area) trade-off analysis, reliability mechanism design, transistor-level simulation, cross-functional technical execution
Preferred skills
HBM/DDR/LPDDR/GDDR experience, silicon bring-up, failure analysis
Technologies
HSPICE, Spectre, FineSim, PrimeSim
Responsibilities
Define HBM core-die architecture (Bank/Bank-Group, array partitioning, datapath, refresh); Drive timing closure for row/column/sensing/datapath paths; Develop ARDs including golden schematics and timing budgets; Lead feasibility studies using transistor-level simulation; Collaborate with Array, Datapath, ECC, TSV, PDN, Layout, Verification, and DFT teams; Support silicon bring-up and failure analysis.