Senior HBM Architecture & Circuit Design Engineer
Core
Own next-generation HBM core-die architecture and critical DRAM circuit design to define bandwidth, power, area, thermal efficiency, and reliability for 3D-stacked memory products.
Role type
Senior IC HBM Architecture & Circuit Design Engineer
Builds
Advanced 3D-stacked HBM products and Architecture Reference Designs (ARD)
Domain
Semiconductor / Memory / High Bandwidth Memory (HBM)
Required skills
DRAM architecture design, DRAM circuit design, SPICE-based circuit simulation, PPA trade-off analysis, silicon bring-up, cross-functional technical execution
Preferred skills
HBM/DDR/LPDDR/GDDR experience, transistor-level simulation, physical implementation analysis
Technologies
HSPICE, Spectre, FineSim, PrimeSim
Responsibilities
Own HBM core-die architecture including Bank/Bank-Group organization, array partitioning, datapath, refresh, and reliability features; Drive critical DRAM circuit design and timing closure for row, column, sensing, and datapath paths; Develop and optimize architecture solutions for bandwidth, power, area, thermal, and reliability trade-offs; Define and validate refresh, row-hammer mitigation, data-retention, and power-efficient operation schemes; Lead architecture feasibility studies using transistor-level simulation and physical implementation analysis; Develop HBM Architecture Reference Designs (ARD), including golden schematics, timing budgets, and verification methodology; Collaborate with Array, Datapath, ECC, TSV, PDN, Layout, Verification, and DFT teams to drive end-to-end design execution; Support silicon bring-up, characterization, failure analysis, and architecture-to-design handoff