NAND Designer / Layout
Core
Develop, integrate, and optimize custom test circuit architectures for NAND flash memory designs, including transistor-level digital, analog, mixed-signal, monitoring, control, and memory-array interface circuits.
Role type
Senior IC analog/mixed-signal circuit designer (test architecture)
Builds
Custom test circuits, test sequences, and test modes for NAND flash memory
Domain
Semiconductor / Memory / Analog & Mixed-Signal Design
Required skills
Transistor-level circuit design, Analog circuit design, Mixed-signal design, Silicon debugging, XA simulation, Verilog, Python scripting, Layout-dependent effect analysis, Testability analysis, Risk evaluation (EM/IR, leakage, contention)
Preferred skills
NAND flash memory architecture knowledge, Wafer/package level testing, Oscilloscope/Logic analyzer usage
Technologies
XA, Verilog, Python, Mixed-signal validation environments
Responsibilities
Define circuit functionality, interfaces, and validation criteria based on product specs; Create and optimize schematics, device sizing, bias structures, and multiplexers; Validate circuits using XA and Verilog simulations; Collaborate with layout teams on matching, parasitics, and guard rings; Evaluate risks like leakage, contention, and power sequencing; Develop test sequences and modes for wafer/package levels; Apply AI-assisted workflows for automation and root-cause investigation; Document methodologies and technical recommendations.
Seniority
Mid-Senior, hands-on IC
