Sr Engineer, TSE-DRAM
Core
Develop, debug, and maintain code for parallel testing of advanced DRAM memory devices, optimizing test flows and algorithms to reduce product test times and manufacturing costs.
Role type
Senior IC semiconductor test engineer (DRAM)
Builds
Production test programs, test algorithms, and DFT/DFM/DFR capabilities for DRAM products
Domain
Semiconductor manufacturing / Memory testing
Required skills
C++ programming, Python scripting, Unix/Linux command line, Statistical Process Control (SPC), Data analysis, CMOS manufacturing knowledge, DRAM device physics, ATE platforms, Algorithm pattern generation (APG)
Preferred skills
Digital logic gates, CMOS transistor operation, Design for Test (DFT), Design For Manufacturability (DFM), Design For Reliability (DFR)
Technologies
C++, Python, Perl, Unix/Linux, ATE platforms
Responsibilities
Design test plans and algorithms for DRAM covering defect coverage and characterization; Develop and release test programs to manufacturing areas; Automate test processes and develop tools for probe data analysis; Independently debug test issues and identify root causes; Provide statistical data analysis to evaluate yields and quality; Lead teams in developing new processes and capabilities to support product roadmap.
Seniority
Senior, hands-on IC
