FY27 Intern - Camera Design Implementation Intern - Canada (16 months)
Core
Developing implementation infrastructure for Camera IP delivered to various SoCs, working from RTL integration through physical design.
Role type
Intern, ASIC Design Implementation Engineer
Builds
Camera cores (Spectra ISP) for Snapdragon SoCs
Domain
Semiconductor / ASIC Design
Required skills
RTL synthesis, static timing analysis, formal verification, physical design, ECO generation, low power synthesis, scripting for automation
Preferred skills
Understanding of ASIC design flow, advanced deep sub-micron technologies
Technologies
Synthesis tools, Static Timing Analysis (STA) tools, Formal Verification tools, Physical Design tools, ECO tools
Responsibilities
Execute RTL to GDS2 flow including synthesis, STA, formal verification, and physical design; Integrate and deliver Camera cores from RTL to Netlist; Identify areas for flow and process improvements; Perform RTL synthesis using physically aware tools; Conduct formal verification and low power verification; Close design timing via STA and constraints development; Generate and verify ECOs for functional and timing fixes; Automate flows using scripting.
