Staff IC Packaging Engineer - Mechanical Simulation
Core
Develop mechanical FEA models and perform stress/mechanical analysis for IC package designs and failure prediction using ANSYS APDL and Workbench.
Role type
Staff IC mechanical simulation engineer (packaging)
Builds
IC chipsets and advanced packaging technologies
Domain
Semiconductor / IC microelectronic packaging
Deliverable
production ML models
Required skills
Finite Element Analysis (FEA), ANSYS APDL, ANSYS Workbench, sub-modeling, contact analysis, non-linear analysis, material characterization, solder joint reliability (SJR) prediction, chip package interaction (CPI) analysis, warpage analysis, design of experiments (DOE), thermo-mechanical behavior analysis
Preferred skills
PhD in Mechanical/Materials/Electrical Engineering, 6+ years FEA experience, 3+ years ANSYS experience, 4+ years semiconductor packaging experience, AI tools for simulation workflows
Technologies
ANSYS APDL, ANSYS Workbench
Responsibilities
Develop mechanical FEA models, maintain APDL macros/workflows, establish FEA methodologies for test correlation, perform stress/mechanical analysis for IC package designs, conduct failure prediction, execute warpage/stress analysis, predict solder joint reliability, simulate package assembly processes, analyze chip package interaction (CPI)
Seniority
Staff, hands-on IC