Senior Emulation Performance Methodology & Debug Engineer
Core
Developing and supporting pre-silicon emulation platforms for SoC designs, focusing on methodology creation, hardware bring-up, and system-level debugging.
Role type
Senior IC emulation performance methodology & debug engineer
Builds
Pre-silicon emulation platforms (FPGA, Veloce, Palladium) and debug workflows for SoC designs
Domain
Semiconductor hardware design (ASIC/SoC) and FPGA prototyping
Required skills
Emulation platforms (FPGA, Veloce, Palladium), SystemVerilog/Verilog, C programming, Python/TCL scripting, FPGA timing closure, JTAG/kernel debugging, SoC architecture (CPU/DSP, NoC, PMIC, Interconnects), Digital circuit validation
Preferred skills
Cross-site collaboration, Vendor engagement, Executive communication, Pre-silicon enablement, Low-level software/hardware debugging, Power/performance analysis
Technologies
Xilinx/Intel FPGAs, Synthesis/Place & Route tools, Waveform generation tools, JTAG debuggers, Kernel debuggers
