CPU Physical Design CAD Engineer (Sr Staff)
Core
Build and support high-performance place-and-route CAD flows and implementation tools for custom CPUs to ensure industry-leading power, performance, and area.
Role type
Sr Staff IC CPU Physical Design CAD Engineer
Builds
High-performance place-and-route CAD flows and implementation tools for custom CPUs
Domain
Semiconductor / CPU Physical Design
Required skills
Place-and-route methodology, Tcl, Python, automation, physical design tasks (timing sign-off, PDV), advanced technology nodes (5nm or lower), digital design, timing analysis, physical verification, industry-standard place-and-route tools (e.g., Cadence Innovus)
Preferred skills
Masters degree in EE/CS, 10+ years in place-and-route of high-performance chips, experience with regression of place-and-route flows
Technologies
Cadence Innovus, Tcl, Python
Responsibilities
Develop, integrate and release new features in high-performance place-and-route CAD flow; Architect and recommend methodology improvements to ensure best PPA; Maintain, support and debug implementation flows; Work with EDA vendors to define roadmap and resolve tool issues
Seniority
Sr Staff, hands-on IC
