SoC Infrastructure/NoC, Power & Performance Validation Engineer, Staff
Core
Develop, validate, and scale system-level test content for SoC bus architecture, performance, and power across pre- and post-silicon phases.
Role type
Staff SoC Infrastructure/NoC, Power & Performance Validation Engineer
Builds
Premium mobile, flagship, data center, and AI accelerator SoCs
Domain
Semiconductor / SoC Validation
Deliverable
production ML models
Required skills
NoC/Interconnect architecture (AXI, AHB), Memory hierarchy and caches, CPU/DDR concepts, Power management (DVFS, low power modes), Debug architecture (JTAG), Performance counters/telemetry, C/C++/Python/Assembly, Embedded systems
Preferred skills
AI/ML accelerators, Tensor operations, Transformer models, System-level debug, Silicon bring-up
Technologies
JTAG, Perfmon, AXI, AHB, DDR, GPU, Multimedia
Responsibilities
Develop performance validation plans and analyze Power-Performance trade-offs, Analyze SOC Bandwidth, QoS, Latency and Throughput, Evaluate AI inference and training workloads for throughput/latency/memory/power efficiency, Create performance dashboards and technical reviews for leadership
Seniority
Staff, hands-on IC
