SOC Debug Engineer
Core
Define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development for high performance, high quality, low power world class products, with a focus on SoC control, boot, reset, timebase management, debug, and micro-controllers.
Role type
Senior IC SoC Architect (Debug & Security)
Builds
Next-generation system-on-chip (SoC) products across compute, automotive, mobile, wearables, XR, and IoT, utilizing RISC-V architecture.
Domain
Semiconductor / Hardware Engineering / SoC Architecture
Required skills
SoC architecture design, ARM and RISC-V AP architecture, silicon design principles, trade-off analysis, cross-level abstraction (system-design to silicon), architectural specification generation, C++/Python programming for modeling and automation, functional and performance simulation, hardware/software interface design.
Preferred skills
Security architecture, system-level debug, boot and reset architecture, timebase management, micro-controllers, BMC/ECU components, heterogeneous compute, NoC/interconnect, memory-systems, multicore, multi-die, cache hierarchies, high-speed I/O (USB, PCIe, CXL), external memory architectures (LPDDR, NAND Flash), networking (Ethernet, WLAN, Cellular, CAN), real-time operating systems (Zephyr, FreeRTOS), AI/ML integration.
Technologies
RISC-V, ARM (Cortex-A/R/M, CoreSight), C++, Python, functional simulators, performance profilers, LPDDR, NAND Flash, NOR Flash, USB, PCIe, CXL, Ethernet, WLAN, Cellular, CAN, Android, Linux, Windows, Zephyr, FreeRTOS.
Responsibilities
Create highly scalable SoC architecture with expertise in SoC control, boot, reset, timebase management, debug, and micro-controllers; comprehend product requirements to steer generation of proper architecture; perform trade-off analysis in the solution space to produce the most optimal architecture; collaborate with architects, technical leads, hardware and software engineers to derive architectural solutions; generate detail architectural specification and work closely with design team to implement the architecture.
Seniority
Senior, hands-on IC
