Staff Engineer - SoC Power Architecture
Core
Drive power-efficient architectures for next-generation System-on-Chips (SoCs) by optimizing dynamic power, Vmin reduction, leakage power, and energy footprint across SoC infrastructure.
Role type
Staff SoC Power Architect
Builds
Next-generation SoCs with optimized power performance and energy efficiency
Domain
Semiconductor / SoC Design / Power Architecture
Required skills
SoC Power Architecture, Dynamic Power Optimization, Vmin Analysis, Leakage Power Reduction, Low-Power Design Techniques, PDN/Power Integrity Analysis, DVFS, Clock Gating, Power Gating, MATLAB Modeling, SPICE Simulations
Preferred skills
Lab characterization of SoC infra energy impacts, Data analysis, Cross-functional technical evaluation
Technologies
MATLAB, SPICE
Responsibilities
Explore new SoC-level power architecture and optimization features; Conduct energy and latency sensitivity studies for power reduction techniques; Analyze and optimize Vmin margins and power-performance tradeoffs; Drive leakage reduction and low-power design techniques across advanced process nodes; Evaluate techniques to manage voltage droops, overshoots, thermal, and electrical limits; Develop MATLAB models to quantify PPA KPIs; Perform SPICE simulations to backup architecture features.
