Power Engineer
Core
Define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development for high performance, high quality, low power world class products.
Role type
ASIC RTL power optimization engineer
Builds
Digital and/or analog IP blocks and SoCs for Qualcomm's high-performance, low-power products
Domain
Semiconductor / ASIC Design / Low-power electronics
Required skills
RTL power optimization, PowerArtist/PTPX/PowerPro tools, low-power design techniques (clock gating, power gating), backend flows (logic synthesis, place-and-route), Python programming, debugging RTL/gate-level power anomalies
Preferred skills
Emulation power flow methodology, AI/ML-driven analysis flows
Technologies
PowerArtist, PTPX, PowerPro, Python
Responsibilities
Collaborate with cross-functional groups to determine product execution path; debug RTL or gate-level power anomalies and identify root-cause structures; build automation scripts and data pipelines for power optimization
Seniority
Mid-level, hands-on IC
