Senior Emulation Performance Methodology & Debug Engineer
Core
Develop and support pre-silicon emulation platforms for System-on-Chip (SoC) designs, focusing on performance methodology, build generation, and debugging.
Role type
Senior IC emulation performance and debug engineer
Builds
Pre-silicon emulation platforms and prototypes for SoC designs
Domain
Semiconductor hardware design (ASIC/SoC) and FPGA prototyping
Required skills
Emulation platforms (FPGA, Veloce, Palladium), SystemVerilog, Verilog, C programming, Python, TCL scripting, JTAG debugging, SoC architecture (CPU/DSP, NoC, interconnects), FPGA timing closure
Preferred skills
Cross-site collaboration, vendor engagement, executive communication, pre-silicon bring-up, low-level software/hardware debugging, power and performance analysis, Xilinx/Intel FPGA expertise
Technologies
Veloce, Palladium, Xilinx FPGAs, Intel FPGAs, JTAG, SystemVerilog, Verilog, Python, TCL
Responsibilities
Design and deploy global methodologies for emulation build generation and debug across FPGA platforms; Bring up new FPGA emulation/prototyping hardware and software; Debug low-level software and hardware issues using tools like JTAG and kernel debuggers; Validate and debug digital circuits; Collaborate with architects, designers, and verification engineers on SoC pre-silicon platforms
Seniority
Senior, hands-on IC
