RISCV CPU Design Verification Principal Manager/ Engineer
Core
Develop and execute verification plans for high-performance, low-power RISC-V based CPU designs using simulation and formal verification methodologies.
Role type
Principal Manager/Engineer, CPU Design Verification
Builds
RISC-V CPU cores and SoC components
Domain
Semiconductor Hardware, CPU Architecture
Required skills
CPU architecture and micro-architecture knowledge, simulation and formal verification, C/C++ and scripting, Verilog/SystemVerilog, emulation and FPGA platforms, power management verification (clock gating, power gating, UPF, DVFS), debug and triage of simulation/emulation/silicon failures
Preferred skills
Experience with x86/ARM/MIPS/POWER architectures, in-depth knowledge of digital logic design and DFT architecture, advanced verification techniques, structural debug concepts (JTAG, IEEE1500, MBIST)
