Digital Design Verification Engineer, Staff
Core
Own end-to-end verification of new features and optimizations for high-speed SerDes IP supporting next-generation protocols like Ethernet and PCIe for High-Performance Compute and Data Center applications.
Role type
Staff Digital Design Verification Engineer (ASIC)
Builds
High-performance, high-quality, low-power world-class products (SerDes IP)
Domain
Semiconductors / High-Speed Interconnects
Required skills
ASIC design verification, Verilog/SystemVerilog, UVM, constrained-random verification, formal verification, power-aware verification, Python, Perl, C/C++, EDA tools, Linux/Unix scripting
Preferred skills
Ethernet, PCIe, SerDes PHY, DSP, mixed-signal IP
Technologies
Verilog, SystemVerilog, UVM, Python, Perl, C, C++, GNU Make, EDA tools
Responsibilities
Own end-to-end verification of new features and optimizations, Verify designs supporting next-generation protocols, Prove designs for function, performance and power, Employ AI-enabled tools to accelerate development, Assess design requirements and devise verification plans, Build/enhance testbenches and analyze simulation failures, Integrate 3rd party VIPs for compliance testing, Contribute to continuous improvement of verification methodologies, Lead, plan, and coordinate tasks with team members, Support post-silicon validation and bring-up activities
Seniority
Staff, technical leadership
