Staff Engineer – Synthesized Model IP Design
Core
Develop and deliver synthesized IP models for emulation and FPGA prototyping platforms to support ASIC/SoC design and validation.
Role type
Staff IC ASIC/SoC IP Design Engineer
Builds
Synthesizable RTL IP models, C/C++ reference models, and FPGA prototypes for emulation platforms
Domain
Semiconductor Hardware Engineering (ASIC/SoC/FPGA)
Required skills
RTL design (Verilog/SystemVerilog), C/C++ programming, FPGA implementation, emulation technologies, architecture definition, project planning, technical mentorship
Preferred skills
Large-scale SoC prototyping, multi-FPGA partitioning, AI-assisted design methodologies, HLS methodologies, cloud-based EDA workflows
Technologies
Xilinx UltraScale+/Versal, Vivado, Siemens Veloce, Cadence Zebu, Palladium, AXI/AHB/APB, LPDDR5/6, PCIe, Ethernet, USB, MIPI
Responsibilities
Lead design and development of synthesizable IP models; Contribute to architecture and micro-architecture definition; Develop and optimize RTL implementations; Develop and maintain C/C++ reference models; Drive IP integration, debug, and validation across simulation/emulation/FPGA; Support FPGA implementation and hardware bring-up; Mentor engineers and drive adoption of automation/AI methodologies
Seniority
Staff, hands-on IC with technical leadership
