Package Manufacturing Engineer, Senior to Staff Level (Kaohsiung or Taichung)
Core
Senior to Staff level Package Manufacturing Engineer supporting development of products and advanced technologies for Qualcomm bumping, WLP, Flip Chip CSP, BGA, SiP, EMIB, CoWoS, CPO, Data center, ASIC, Server, and 2.5/3D Chiplet applications.
Role type
Senior to Staff IC Package Manufacturing Engineer
Builds
Semiconductor packaging and assembly products for data center, server, and advanced chiplet applications
Domain
Semiconductor Manufacturing / Advanced Packaging
Required skills
Semiconductor packaging engineering, substrate and assembly process details, SPC, Control plans, OCAPs, FMEAs, PCN, CARs, yield management, continuous improvement, assembly cycle time analysis, cost reduction, failure analysis methodology, JMP data analysis, Excel VBA, Tableau
Preferred skills
Quality concept and RMA process, foundry process knowledge, wafer bumping, laser grooving, wafer saw, Pick and place, underfill, Heat spread processes, yield management software (O+), assembly and test house working model, supply chain and KPI
Technologies
JMP, Excel, VBA, Tableau, O+
Responsibilities
Work cross-functionally with Design, Device process development, and Packaging groups; Support product material and design selections; Develop technical risk assessments and mitigation plans; Understand substrate and assembly process details; Analyze yield and assembly cycle time.
Seniority
Senior to Staff, hands-on IC
